1. Field
This disclosure relates generally to semiconductor device testing, and more specifically, to a method for generation, placement, and routing of test structures or device layouts in test chips.
2. Related Art
Early technology development for a given semiconductor technology generally requires a test mask for device exploration and characterization. In particular, many variations of test structures are often required for analog and BiCMOS devices. For example, variations may include over five hundred (500) 2×15 pad array structures that can contain six to twelve (6-12) test structures or devices each. Since the test chips are expensive to produce, repeatability and accuracy of test structure generation, placement, and routing in the arrays are desired. However, no previously known solutions have been effective in addressing these needs. Prior known methods have often required a user to provide extensive information regarding the structure, placement and routing for every test structure of a test chip. Such methods are tedious for the user and furthermore do not leverage known patterns.
FIG. 1 is a flow diagram view 10 of a prior known method of generating, placing and routing of test structures for test chips. Upon an initiation of the method, at step 12, the tool set receives extensive information input. The information can be a combination of the following: cross-sections, parameterized cells and geometry values for the structure or design rule values that define the structure layout, schematics and geometry values for the corresponding structure. In response to receiving the input at step 12, the process continues at step 14 with a generation operation. The generation operation includes creating multiple test structure layout variations based on the geometry values.
In step 16, the method requires user specified information detailing the placement of the test structure within the pad array or test array. User specified information relates to (i) how terminals on the test structure need to be routed and (ii) where the test structure is placed within a pad or bit array structure. This procedure is quite cumbersome for a user and must be repeated for each test structure or test type of a given test chip. The method then proceeds to step 18.
In step 18, a user provides logistical information such as the physical location of the test structures being generated, any naming specifications and related details. This may be processed via a graphical user interface.
In step 20, responsive to data created by the generation operation and required user specified placement and routing information, the method generates test structures placed and routed within one or more pad or bit arrays. The generated test structure layouts typically require assembly within a fabricated test die and quality assurance verification. The test structures (or other input data) may be further utilized to drive testing equipment once the layouts are fabricated on wafers. Thereafter, the method ends.
The method described with respect to FIG. 1 suffers from various disadvantages. For example, the method does not address efficiency, wherein the user must specify generation, placement and routing information in a tedious manner. In addition, various steps in the method of FIG. 1 are not completely independent. For example, if generation information changes, such as device geometries or device layouts, then the placement and routing steps must be repeated. Still further, the method of FIG. 1 does not address repeatability in that if devices are similar in placement and routing requirements, then the user must still specify all information for each test structure for every technology. As a result, the methodology of FIG. 1 is inefficient, and thus making it difficult to maintain and use.
Accordingly, there is a need for an improved method for overcoming the problems in the art as discussed above.